Signal Processing Magic (3) -- Farrow Structure

Farrow structure was invented by C. W Farrow. It minimizes the number of multiplication used in fractional interpolation. Farrow structure is often deployed when there is fractional sampling rate change in the signal path. For example, ADC rate is set as 120MHz but baseband signal processing only supports 100MHz. Therefore, a filter needs to be designed for supporting rate conversion from 120MHz to 100MHz. Farrow structure is one candidate for this kind of job.

The setting of Farrow depends on the polynomial it supports. Let us take an example of using cubic Lagrange for fractional interpolation. The output y[n] can be written as combination of input x[n] as:
$$y[n]=C_{-2}x[n-2]+C_{-1}x[n-1]+C_{0}x[n]+C_{1}x[n+1]$$

Assuming fractional delay is $\tau$, using Lagrange formula, $C_{-2}$ equals to the division of $(-\tau-(-1))(-\tau)(-\tau-1)$ by $(-2-(-1))(-2)(-2-1)$. Thus,
$$C_{-2}=\frac{\tau^{3}}{6}-\frac{\tau}{6}$$
Extend the same formula to other coefficients, we have
$$C_{-1}=-\frac{\tau^{3}}{2}+\frac{\tau^{2}}{2}+\tau$$
$$C_{0}=\frac{\tau^{3}}{2}-\tau^{2}-\frac{\tau}{2}+1$$
$$C_{1}=-\frac{\tau^{3}}{6}+\frac{\tau^{2}}{2}-\frac{\tau}{3}$$
Rewriting the y[n] equation, we have
$$y[n]=\frac{1}{6}[(x[n-2]-3x[n-1]+3x[n]-x[n+1])\tau^{3}+ \\ (3x[n-1]-6x[n]+3x[n+1])\tau^2+ \\ (-x[n-2]+6x[n-1]-3x[n]-2x[n+1])\tau+6x[n]]$$

Corresponding Farrow structure is shown below. It only needs three multipliers and $\tau$ is input to all multipliers. This simplifies the hardware design. When polynomial is different, the coefficients of FIR filter change accordingly. We should also note that due to the difference between input and output rates, one input sample not necessarily generates one output sample. A control logic is needed to dictate when to generate outputs.

Signal Processing Magic (2) -- Sigma Delta ADC

Sigma Delta ADC is a commonly used architecture for converting analog signal to digital. The conception of ADC is quite simple: let us say we have 4 bits with bit3 representing 1volt, bit2 for 0.5 v, bit1 for 0.25v and bit0 for 0.125v, I can quantize an analog input in volt to these 4 bits. For example, if the input is 1.2 volts, then it becomes [bit3 bit2 bit1 bit0] = [1010] = 1.25v. The quantization error is equal to 1.2-1.25 = -0.05v. Quantization noise comes from quantization error. A straightforward thought is to use binary search to convert analog input to digital. This is the basic idea behind SAR (Successive Approximation Register) ADC. 

Sigma Delta ADC, our main topic in this article, is constructed differently. Assuming x(n) is the input and y(n) is the output of sigma delta modulator, y(n) has a much higher sampling rate than x(n) and y(n) is also only 1 bit. So in term of y(n), sigma delta can be seen as a trade off between sampling rate and bitwidth. y(n) will then pass through lowpass filter and decimator to produce the multiple-bit ADC output we commonly work with.

Now let us do some math to figure out what really happens in sigma delta. First we calculate the transfer function between v(n) and u(n)

$$z^{-1}(U(z)+V(z))=V(z)$$
which gives
$$H(z)=\frac{V(z)}{U(z)}=\frac{z^{-1}}{1-z^{-1}}$$

The transfer function from input, x(n), to output, y(n), is equal to
$$\frac{Y(z)}{X(z)}=\frac{H(z)}{1+H(z)}=z^{-1}$$
which tell us there is signal delay but no signal distortion.

e(n) added to 1-bit ADC in the diagram represents quantization noise. The transfer function from e(n) to y(n) is
$$\frac{Y(z)}{E(z)}=\frac{1}{1+H(z)}=1-z^{-1}$$
Frequency response of Y(z)/E(z) is shown below. Its amplitude increases with frequency which means sigma delta modulator pushes out noise from in-band to out-of-band. Reducing in-band noise level is the major benefit of sigma delta. What we discussed here is first-order sigma delta. If we goes to higher order sigma delta, the in-band noise level will be further reduced but the cost paid is more sophisticated hardware and higher out-of-band noise level.

Signal Processing Magic (1) -- CIC Filter

In the world of signal processing, there are many elegant schemes. They are beautiful and pragmatic at the same time. Sometime you are wondering how the inventors create them. I feel obliged to introduce them to my audience. Today, let me start from a filter named CIC (Cascaded Integrator–Comb). CIC filter is mainly used for integer up-sampling and down-sampling. The main benefit of this scheme is that no multiplication is needed, which is welcomed in term of hardware complexity.

Figure below shows CIC filter architecture with N stages and decimation rate of R. M is an extra parameter and it can be 1 or 2. Normally M is set as 1. CIC filter can also be used as interpolation and the flow is opposite when used as decimation.

Accordingly, we can write the transfer function of decimation CIC filter as:

$$(\frac{1-z^{-RM}}{1-z^{-1}})^{N}$$


By increasing N with fixed R, the filter can have more rejection.

By increasing R with fixed N, the filter's cutoff frequency decreases proportionally.